Cadence數字前端設計筆試題2018
源自微信公眾號 「數字晶元實驗室」
1、 What is the minimum number of flip flops to implement a state machine to detect the bit sequence 11011001 ?
A.8 B.3 C.4 D.6
狀態機時序圖如下，一共有9個狀態，最少使用4個觸發器。
2、 What types list below could be used in packed array ?
A.Bit http://B.int C.logic D.reg
System Verilog 語法
3、 Divide (1110111)2 by (1001)2
A Quotient (1101)2 remainder (10)2
B. Quotient (1101)2 remainder (0)2
C. Quotient (10)2 remainder (0)2
D. Quotient (1101)2 remainder (101)2
4、 What is the duration of task t ? (模擬持續時間)
A . 10 time units
B. 16 time units
C . 5 time units
D . 7 time units
Systemverilog 語法 （fork-join、fork-join_none、fork_noin_any）
5、 According to the following truth table with input A,B,C and D, what is an equation for output F ?
D (排除法，卡諾圖化簡)
6、 What input can detect stuck at -1 fault at E ?
A (DFT 相關)
D= 1 C= 0 ,使得 Y = E = A&&B ,通過A選項輸入，如果 Y = 1，則E stuck at 1
7、 Given the following design ,What are the effective setup and hold times for the following circuit ?
A. Tsetup = 4ns, Thold = 1ns
B. Tsetup = 3ns, Thold = 0ns
C. Tsetup = 3ns, Thold = 1ns
D. Tsetup = 2ns, Thold = 0ns
Setup分析 :
D 觸發器：
增加數據路徑異或門延時：
增加數據路徑異或門延時+ 時鐘路徑反相器延時
Tsetup = 2ns + 2ns – 1ns = 3ns
Hold分析 :
D 觸發器：
增加數據路徑異或門延時：
增加數據路徑異或門延時+ 時鐘路徑反相器延時
Thold = 2ns – 2ns + 1ns = 1ns
8、 What is the maximum operating frequency of the above circuit ? (第7題)
A 250MHZ B 80MHz C 125 MHz D 166.7MHz
針對第7題的設計，Tskew = 0
T – Tcq – Tlogic – T setup >= 0
Tcq + Tlogic >= Thold
T >= 8ns ,Fmax = 125 M
9、 Which equation best describes the maximum clock frequency in a synchronous system ?
D 同上題
10、 Given the following design ,What is the setup margin for flop2 ?
A 8.95ns B 9.55ns C 0.85ns D 7.75
F2setup margin = 10ns – 0.65ns – 0.35ns - 0.45ns + 0.6ns – 0.2ns = 8.95ns
11、 What is the hold margin for flop2 ?
A 0.5ns B 0.1ns C -0.1ns D 9.9ns
F2hold margin = 0.25ns + 0.15ns – 0.4ns - 0.1ns = -0.1ns
12、 Design a module in Verilog to satisfy the following requirements.
(1) A clock with the frequency of 100MHz
(2) A 4-bit width signal that sensitive at the clock posedge ,constrain this signal to be randomized 16 times in the range from 8 to 15.
沒有使用System verilog 語法
13、What is logic systhesis ?
邏輯綜合是將RTL代碼，進行翻譯+ 優化 + 映射，生成特定工藝庫相關的門級網表，用於後端的佈局布線
14、What is function verification ?
功能驗證，用來驗證設計的邏輯功能是否正確。
15、What is formal verification ?
形式驗證，使用靜態窮舉的方式驗證電路。主要是用來驗證電路經過邏輯綜合，佈局布線之後的邏輯等價性。
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