Verilog重點解析（加法器，減法器）
源自：微信公眾號 「數字晶元實驗室」
1bit全加器代碼：
module full_adder(
input a,b,cin ,
output s,cout
);
assign {cout,s} = a + b + cin ;
endmodule
模擬：
`timescale 1ns/1ns
module full_adder_tb;
reg a,b,cin ;
wire s,cout ;
initial begin
a = 0 ;
b = 0 ;
cin = 0 ;
#100 ;
$stop ;
end
always #10 a = $random%2 ;
always #10 b = $random%2 ;
always #10 cin = $random%2 ;
full_adder DUT(
.a(a),
.b(b),
.cin(cin) ,
.s(s),
.cout(cout)
);
endmodule
4位全加器：
module adder_4bit_4(
input [3:0] a ,b ,
input cin ,
output [3:0] s ,
output cout
);
wire [2:0] co ;
/* instantiate 1 bit adder */
full_adder full_adder_u0(
.a(a[0]),
.b(b[0]),
.cin(cin) ,
.s(s[0]),
.cout(co[0])
) ;
full_adder full_adder_u1(
.a(a[1]),
.b(b[1]),
.cin(co[0]) ,
.s(s[1]),
.cout(co[1])
) ;
full_adder full_adder_u2(
.a(a[2]),
.b(b[2]),
.cin(co[1]) ,
.s(s[2]),
.cout(co[2])
) ;
full_adder full_adder_u3(
.a(a[3]),
.b(b[3]),
.cin(co[2]) ,
.s(s[3]),
.cout(cout)
) ;
endmodule
模擬：
module adder_4bit_4_tb;
reg [3:0] a ,b ;
reg cin ;
wire [3:0] s ;
wire cout ;
adder_4bit_4 DUT (
.a(a) ,
.b(b) ,
.cin(cin) ,
.s(s) ,
.cout(cout)
);
initial begin
a = 4b0 ;
b = 4b0 ;
cin = 1b0 ;
#100 ;
$stop ;
end
always #10 a = $random%16 ;
always #10 b = $random%16 ;
always #10 cin = $random%2 ;
endmodule
4位加減法器 ：
根據： a – b = a + (-b)
代碼：
module addsub_4bit(
input [3:0] a ,b ,
input cin ,
input sub , //1 :sub ; 0 : add
output [3:0] s ,
output cout
);
wire cin_pre = cin ^ sub ;
wire [3:0] b_pre = b ^ {4{sub}} ;
wire [2:0] co ;
full_adder full_adder_u0(
.a(a[0]),
.b(b_pre[0]),
.cin(cin_pre) ,
.s(s[0]),
.cout(co[0])
);
full_adder full_adder_u1(
.a(a[1]),
.b(b_pre[1]),
.cin(co[0]) ,
.s(s[1]),
.cout(co[1])
);
full_adder full_adder_u2(
.a(a[2]),
.b(b_pre[2]),
.cin(co[1]) ,
.s(s[2]),
.cout(co[2])
);
full_adder full_adder_u3(
.a(a[3]),
.b(b_pre[3]),
.cin(co[2]) ,
.s(s[3]),
.cout(cout )
);
endmodule
模擬：
module addsub_4bit_tb;
reg [3:0] a ,b ;
reg cin ;
reg sub ;
wire [3:0] s ;
wire cout ;
addsub_4bit DUT(
.a(a) ,
.b(b) ,
.cin(cin) ,
.sub(sub) ,
.s(s) ,
.cout(cout)
);
initial begin
a = 4b0 ;
b = 4b0 ;
cin = 1b0 ;
sub = 1b0 ;
#100 ;
$stop ;
end
always #10 a = $random%16 ;
always #10 b = $random%16 ;
always #20 cin = $random%2 ;
always #20 sub = $random%2 ;
endmodule
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