數字IC筆試題(5)-全志科技數字前端 排除法即可。 B、施密特觸發C、方波增強抗干擾能力,避免誤觸發。 列出所有情況A[3:0] = 4』b0000 ~ 4』b1111即可 rst_n為非同步複位,然後在每個上升沿進行觸發器狀態更新 建立時間:Clk_delay_ff2 + T > Clk_delay_ff1 + Tco + Tcomb + Tsetup 0.8ns + 4ns > 1ns + 1.2ns + 2.2ns + 0.6ns 4.8ns > 5ns,所以建立時間不滿足保持時間: Clk_delay_ff1 + Tco+ Tcomb > Clk_delay_ff2+ Thold 1ns + 1.2ns + 2.2ns > 0.8ns + 0.3ns 4.4ns > 1.1ns,所以保持時間滿足 divider.v,所謂分頻器就是計數器的輸出狀態,奇數分頻器需要同時用到上升沿和下降沿。module divider( input clk , input rst_n , input [2:0] divider_num , output reg out_clk ); reg [2:0] divider_num_reg ; always@(posedge clk or negedge rst_n) begin if(!rst_n) begin divider_num_reg <= 0 ; end else begin divider_num_reg <= divider_num ; end end reg [2:0] count ; always@(posedge clk or negedge rst_n) begin if(!rst_n) begin count <= 0 ; out_clk <= 0 ; end else begin count <= count +1 ; if(count == (divider_num_reg-1)) begin out_clk <= ~out_clk ; count <= 0 ; end end end always@(negedge clk or negedge rst_n) begin if(!rst_n) begin count <= 0 ; out_clk <= 0 ; end else begin count <= count +1 ; if(count == (divider_num_reg-1)) begin out_clk <= ~out_clk ; count <= 0 ; end end end endmodule divider_tb.v,根據輸入寄存器控制分頻計數值module divider_tb; reg clk ; reg rst_n ; reg [2:0] divider_num ; wire out_clk; initial begin rst_n = 1 ; #10 rst_n = 0 ; #10 rst_n = 1 ; end initial begin clk = 0 ; forever #5 clk = ~clk ; end initial begin divider_num =1 ; #300 divider_num =2 ; #300 divider_num =3; #300 divider_num =4 ; #300 divider_num =5 ; #300 divider_num =6 ; #300 divider_num =7 ; #300 divider_num =8 ; end divider divider( .clk(clk) , .rst_n(rst_n) , . divider_num(divider_num) , .out_clk(out_clk) ); endmodule shift[2:0] = 3』b000 :output[7:0] = inp(0)_0_0_0_0_0_0_0 shift[2:0] = 3』b001 :output[7:0] = inp(1)_ inp(0)_0_0_0_0_0_0 shift[2:0] = 3』b010 :output[7:0] = inp(2)_ inp(1)_ inp(0)_0_0_0_0_0 shift[2:0] = 3』b011 :output[7:0] = inp(3)_ inp(2)_ inp(1)_ inp(0)_0_0_0_0 shift[2:0] = 3』b100 :output[7:0] = inp(4)_inp(3)_ inp(2)_ inp(1)_ inp(0)_0_0_0 shift[2:0] = 3』b101 :output[7:0] = inp(5)_inp(4)_inp(3)_ inp(2)_ inp(1)_ inp(0)_0_0 shift[2:0] = 3』b110 :output[7:0] = inp(6)_inp(5)_inp(4)_inp(3)_ inp(2)_ inp(1)_ inp(0)_0 shift[2:0] = 3』b111 :output[7:0] = inp(7)_inp(6)_inp(5)_inp(4)_inp(3)_ inp(2)_ inp(1)_ inp(0) 上述電路為純組合邏輯,電路功能直接由真值表可以看出。關於Verilog實現有很多種描述方式: 根據得出的電路功能行為用行為級Verilog描述: shift_mux.v module shift_mux( input [7:0] inp , input [2:0] shift, output reg [7:0] outp ); always@(*) begin case(shift) 3b000: assign outp = {inp[0],7b000_0000} ; 3b001: assign outp = {inp[1],inp[0],6b00_0000} ; 3b010: assign outp = {inp[2],inp[1],inp[0],5b0_0000} ; 3b011: assign outp = {inp[3],inp[2],inp[1],inp[0],4b0000} ; 3b100: assign outp = {inp[4],inp[3],inp[2],inp[1],inp[0],3b000} ; 3b101: assign outp = {inp[5],inp[4],inp[3],inp[2],inp[1],inp[0],2b00} ; 3b110: assign outp = {inp[6],inp[5],inp[4],inp[3],inp[2],inp[1],inp[0],1b0} ; 3b111: assign outp = {inp[7],inp[6],inp[5],inp[4],inp[3],inp[2],inp[1],inp[0]} ; endcase end endmodule shift_mux_tb.vmodule shift_mux_tb; reg [7:0] inp; reg [2:0] shift; wire [7:0] outp; initial begin inp = 0 ; shift = 0 ; end always #10 inp = $random%256 ; always #10 shift = $random%8 ; shift_mux shift_mux( .inp(inp) , .shift(shift), .outp(outp) ); endmodule 行為級Verilog需要經過綜合工具綜合才能成為實際的電路,此時的電路結構就會發生變化,但是功能會一致。 結構級Verilog描述,此時需要例化所有的MUX,然後進行連接。為了防止工具進行優化,可以對所有的MUX或者線網設置keep/don』t_touch interface_change.v module interface_change( input clka , input wra_n, input da , input clkb , output [7:0] db , output wrb ); reg [7:0] data = 0 ; always@(posedge clka) begin if(!wra_n) begin data <= {data[6:0],da} ; end end reg wra_n_reg1 ,wra_n_reg2 ; always@(posedge clkb ) begin wra_n_reg1 <= wra_n ; wra_n_reg2 <= wra_n_reg1 ; end wire wra_n_check ; assign wra_n_check = wra_n_reg1 &&(!wra_n_reg2) ; assign wrb = wra_n_check ; assign db = (wra_n_check == 1b1) ? data : 0 ; endmodule module interface_change_tb ; reg clka ; reg wra_n; reg da ; reg clkb ; wire [7:0] db ; wire wrb ; initial begin clka = 0 ; #3 ; clkb = 0 ; end initial begin wra_n = 1 ; @(posedge clka) wra_n = 0 ; da = $random%2 ; @(posedge clka) wra_n = 0 ; da = $random%2 ; @(posedge clka) wra_n = 0 ; da = $random%2 ; @(posedge clka) wra_n = 0 ; da = $random%2 ; @(posedge clka) wra_n = 0 ; da = $random%2 ; @(posedge clka) wra_n = 0 ; da = $random%2 ; @(posedge clka) wra_n = 0 ; da = $random%2 ; @(posedge clka) wra_n = 0 ; da = $random%2 ; @(posedge clka) wra_n = 1; end always #5 clka = ~clka ; always #10 clkb = ~clkb ; interface_change interface_change ( .clka(clka) , .wra_n(wra_n), .da(da) , .clkb(clkb) , .db(db) , .wrb(wrb) ); endmodule 推薦閱讀: 相关文章 {{#data}} {{title}} {{/data}}